Sep 01, 2017 Thus a finite state machine (FSM) is a model describing the behavior of a finite number of states, the transitions between those states, and actions 1. SERIAL ADDER. The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit by bit. The serial full. A D–flipflop is used as the storage element. For those of you concerned with titles, the serial adder in Figure 2 is a Mealy–type finite state machine. It is a Mealy model because the output S is a function of both the present state z and the inputs A and B. (If it were a Moore model S would effectively be a function of the present state only.).
![Code Code](http://image.reportshop.co.kr/newprimg/652/651330-0002.gif)
1. The problem statement, all variables and given/known data
My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module.
I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits:
Inputs for the shift register are: Si, CLK, Reset
Outputs for the shift register are: So, D7 through D0 (one for each bit of the register)
Also, if anyone can give me a hint as to how I can approach designing a test bench would be extremely helpful.
3. The attempt at a solution
My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module.
I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits:
Inputs for the shift register are: Si, CLK, Reset
Outputs for the shift register are: So, D7 through D0 (one for each bit of the register)
Also, if anyone can give me a hint as to how I can approach designing a test bench would be extremely helpful.
3. The attempt at a solution